M. Karpovsky, "Multilevel Logical Networks," in IEEE Transactions on Computers, vol. 36, no. , pp. 215-226, 1987.
doi:10.1109/TC.1987.1676884
keywords:{time and space complexity of gate arrays; AND-OR implementations of systems of Boolean functions; delays; gate arrays; gate counts; multilevel logical networks},
url:doi.ieeecomputersociety.org/10.1109/TC.1987.1676884