Chao and Gray, "Micro-operation perturbations in chip level fault modeling," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 579-582.
doi:10.1109/DAC.1988.14819
keywords:{logic testing; chip level fault modeling; micro-operation perturbation; stuck-at-fault coverage; combination circuits; gate level coverage},
url:doi.ieeecomputersociety.org/10.1109/DAC.1988.14819