"A global postsynthesis optimization method for combinational circuits," Design, Automation & Test in Europe Conference & Exhibition(DATE), Grenoble France, 2011, pp. 1-4.
doi:10.1109/DATE.2011.5763326
keywords:{logic gates;circuit optimisation;combinational circuits;computability;equivalent circuits;genetic algorithms;logic design;mutated offspring;global postsynthesis optimization;combinational circuit;genetic programming-based circuit synthesis;circuit gates;fitness function;fitness evaluation time;SAT solver;equivalence checking time;parent circuit;Logic gates;Genetic programming;Indexes;Benchmark testing;Runtime;Circuit synthesis;Analog circuits},
url:doi.ieeecomputersociety.org/10.1109/DATE.2011.5763326