@INPROCEEDINGS{,
author = {},
booktitle = {Design, Automation & Test in Europe Conference & Exhibition(DATE)},
title = {A global postsynthesis optimization method for combinational circuits},
year = {2011},
volume = {00},
number = {},
pages = {1-4},
keywords={logic gates;circuit optimisation;combinational circuits;computability;equivalent circuits;genetic algorithms;logic design;mutated offspring;global postsynthesis optimization;combinational circuit;genetic programming-based circuit synthesis;circuit gates;fitness function;fitness evaluation time;SAT solver;equivalence checking time;parent circuit;Logic gates;Genetic programming;Indexes;Benchmark testing;Runtime;Circuit synthesis;Analog circuits},
doi = {10.1109/DATE.2011.5763326},
url = {doi.ieeecomputersociety.org/10.1109/DATE.2011.5763326},
ISSN = {1530-1591},
month={03}
}