TY - CONF
TI - A global postsynthesis optimization method for combinational circuits
T2 - Design, Automation & Test in Europe Conference & Exhibition(DATE)
SP - 1
EP - 4
PY - 2011
KW - logic gates
KW - circuit optimisation
KW - combinational circuits
KW - computability
KW - equivalent circuits
KW - genetic algorithms
KW - logic design
KW - mutated offspring
KW - global postsynthesis optimization
KW - combinational circuit
KW - genetic programming-based circuit synthesis
KW - circuit gates
KW - fitness function
KW - fitness evaluation time
KW - SAT solver
KW - equivalence checking time
KW - parent circuit
KW - Logic gates
KW - Genetic programming
KW - Indexes
KW - Benchmark testing
KW - Runtime
KW - Circuit synthesis
KW - Analog circuits
DO - 10.1109/DATE.2011.5763326
JO - Design, Automation & Test in Europe Conference & Exhibition(DATE)
SN - 978-1-61284-208-0
VO - 10.1109/DATE.2011.5763326
VL - 00
JA - Design, Automation & Test in Europe Conference & Exhibition(DATE)
Y1 - March 2011
ER -